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| JUNE.2001 Rev. 1.1 4-BIT SINGLE CHIP MICROCOMPUTERS GMS36/37XXX(T) SERIES USERS MANUAL * GMS36/37004(T) * GMS36/37112(T) * GMS36/37140(T) Revision 1.1 Published by MCU Application Team in HYNIX Semiconductor Inc. All Right Reserved. Editor's E-Mail : rhja@hynix.com Additional information of this manual may be served by HYNIX Semiconductor Inc.Offices in Korea or Distributors and Representative listed at address directory. HYNIX Semiconductor Inc.reserves the right to make changes to any Information here at any time without notice. The information, diagrams, and other data in this manual are correct and reliable; however, HYNIX Semiconductor Inc.is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. Table of Contents Table of Contents Chapter 1 GMS36XXX ........................................................1-1 .......................................................1-1 .......................................................1-2 .......................................................1-3 .......................................................1-4 .......................................................1-5 .......................................................1-7 .......................................................1-7 .......................................................1-8 Description Features Block diagram Pin assignment Pin description Pin circuit Port operation Optional features Electrical characteristics Chapter 2 GMS37XXX ........................................................2-1 .......................................................2-1 .......................................................2-2 .......................................................2-3 .......................................................2-4 .......................................................2-5 .......................................................2-7 .......................................................2-7 .......................................................2-8 Description Features Block diagram Pin assignment Pin description Pin circuit Port operation Optional features Electrical characteristics Chapter 3 Chapter 4 PACKAGE DIMENSIONS FUNCTIONAL DESCRIPTION .......................................................4-1 .......................................................4-2 .......................................................4-3 .......................................................4-3 .......................................................4-4 .......................................................4-4 .......................................................4-4 .......................................................4-5 .......................................................4-6 .......................................................4-7 .......................................................4-8 ......................................................4-10 ......................................................4-11 Program memory (ROM) ROM address register Data memory (RAM) X-register (X) Y-register (Y) Accumulator (Acc) Arithmetic and Logic Unit (ALU) State Counter (SC) Clock generator Pulse generator Reset operation Watch Dog Timer (WDT) Stop operation Table of Contents Chapter 5 INSTRUCTION ......................................................5-1 ......................................................5-2 ......................................................5-4 Instruction format Instruction table Details of instruction system Chapter 6 APPLICATION ......................................................6-1 ......................................................6-2 ......................................................6-3 ......................................................6-4 ......................................................6-5 ......................................................6-6 .....................................................6-12 .....................................................6-13 Guideline for S/W GMS36112 Circuit diagram GMS37112 Circuit diagram Truth Table for example program Output waveform of uPD6121G Example program-uPD6121G Reference to GMS36XXXT B/D Reference to GMS37XXXT B/D Chapter 7 GMS36XXXT ........................................................7-1 .......................................................7-1 .......................................................7-2 .......................................................7-3 .......................................................7-4 Description Features Pin description Stop operation Electrical characteristics Chapter 8 GMS37XXXT ........................................................8-1 .......................................................8-1 .......................................................8-2 .......................................................8-3 .......................................................8-4 Description Features Pin description Stop operation Electrical characteristics Chapter 9 EPROM Mode define .......................................................9-1 Port define for GMS36XXXT .......................................................9-1 Port define for GMS37XXXT .......................................................9-2 AC/DC timing requirements for program / read mode ...................9-3 Program / verify timing diagrams in kHz version ...................9-4 Program / verify timing diagrams in MHz version ...................9-8 Caution when programming ..................9-14 GMS36XXX GMS37XXX PACKAGE DIMENSIONS FUNCTIONAL DESCRIPTION INSTRUCTION APPLICATION GMS36XXXT GMS37XXXT EPROM 1 2 3 4 5 6 7 8 9 Chapter 1. GMS36XXX 1. GMS36XXX Description The GMS36XXX series are remote control transmitter which uses CMOS technology. This enables transmission code outputs of different configurations, multiple custom code output, and double push key output for easy fabrication. The GMS36XXX series are suitable for remote control of TV, VCR, FANS, Airconditioners, Audio Equipment, Toys, Games etc. Features * * * * * * * * * * * * * * * Program memory : 1,024 bytes for GMS36004/112/140 Data memory : 32 4 bits 43 types of instruction set 3 levels of subroutine nesting Operating frequency : 300kHz ~ 1MHz at kHz version 2.4MHz ~ 4MHz at MHz version Instruction cycle : fOSC/6 at kHz version fOSC/48 at MHz version CMOS process (Single 3.0V power supply) Stop mode (Through internal instruction) Released stop mode by key input (Masked option) Built in Power-on Reset circuit Built in Low Voltage Detection circuit Built in capacitor for ceramic oscillation circuit at kHZ version Built in a watch dog timer (WDT) Built in transistor for I.R LED Drive : IOL =210mA at VDD =3V and VO =0.3V Low operating voltage : 2.0 ~ 3.6V (at 300kHz ~ 4MHz) O Table 1-1 GMS36XXX series members Series Program memory Data memory I/O ports Input ports Output ports Package GMS36004 1,024 32 GMS36112 1,024 32 GMS36140 1,024 32 O4 O4 O4 4 6 (D0~D5) 16DIP/SOP 4 4 6 (D0~D5) 20DIP/SOP/SSOP 4 4 10 (D0~D9) 24Skinny DIP/SOP 1-1 Chapter 1. GMS36XXX Block Diagram VDD GND 24 1 ROM 64word 8 4 8 4 Watchdog timer 10 Program counter 3-level Stack Power-on Reset Low-Voltage Detection O16page O8bit 10 4 08; Instruction Decoder 4 MUX 4 ALU 4 Control Signal 2 X-Reg RAM 16 16word x 2page x 4bit RAM Word Selector4 Y-Reg ACC ST 4 OSC R-Latch 10 D-Latch 4 Pulse Generator 4 4 4 10 I.R. LED Drive Tr. 2 3 6 OSC1 OSC2 7 8 9 K0 ~ K3 10 11 12 13 R0 ~ R3 14 15 16 17 18 19 20 D0 ~ D9 21 5 4 22 23 PGND REMOUT Fig 1-1 Block Diagram (In case of GMS36140) 1-2 Chapter 1. GMS36XXX Pin Assignment GND OSC1 OSC2 K0 K1 K2 K3 D0 1 2 3 4 5 6 7 8 16 VDD 15 REMOUT 14 PGND 13 D5 12 D4 11 D3 10 D2 9 D1 GND 1 OSC1 2 OSC2 3 K0 4 K1 5 K2 6 K3 7 R0 8 R1 9 R2 10 20 VDD 19 REMOUT 18 PGND 17 D5 16 D4 15 D3 14 D2 13 D1 12 D0 11 R3 Fig 1-2 GMS36004 Pin Assignment (16DIP/SOP) Fig 1-3 GMS36112 Pin Assignment (20DIP/SOP/SSOP) GND 1 OSC1 2 OSC2 3 D9 4 D8 5 K0 6 K1 7 K2 8 K3 9 R0 10 R1 11 R2 12 24 VDD 23 REMOUT 22 PGND 21 D7 20 D6 19 D5 18 D4 17 D3 16 D2 15 D1 14 D0 13 R3 Fig 1-4 GMS36140 Pin Assignment (24Skinny-DIP/SOP) 1-3 Chapter 1. GMS36XXX Pin Description Pin VDD GND I/O - Function Connected to 2.0~ 3.6V power supply Connected to 0V power supply. K0 ~ K3 Input 4-bit input port with built in pull-up resistor. STOP mode is released by "L" input of each pin.(masked option) D0 ~ D9 Output Each can be set and reset independently. The output is the structure of N-channel-open-drain. 4-bit I/O port. (Input mode is set only when each of them output "H".) In outputting, each can be set and reset independently(or at once.) The output is in the form of C-MOS. Pull-up resistor and STOP release mode can be respectively selected as masked option for each pin. (It is released by `'L'' input at STOP.) Oscillator input. Input to the oscillator circuit and connection point for ceramic resonator. Internal capacitors available at kHz version. A feedback resistor is internally connected between this pin and OSC2. Connect a resonator between this pin and OSC1. High current output port driving I.R. LED. The output is in the form of N-channel-open-drain. High current Tr. ground pin. (connected to GND) High current output Tr. is connected between this pin and REMOUT. R0 ~ R3 I/O OSC1 Input OSC2 REMOUT Output Output PGND - 1-4 Chapter 1. GMS36XXX Pin Circuit Pin I/O I/O circuit pull-up Note - CMOS output. - "H" output at reset. (Option) - Built in MOS Tr for pull-up, about 140I. R0 ~ R3 I/O pull-up K0 ~ K3 I - Built in MOS Tr for pull-up, about 140I. D0 ~ D9 O - Open drain output. - "L" output at reset. REMOUT O RESET REMOUT - Open drain output. - Output Tr. disable at reset. DATA PGND PGND 1-5 Chapter 1. GMS36XXX Pin I/O STOP I/O circuit Note OSC2 O OSC1 Rd - Built in feedbackresistor about 1 OSC2 - Built in damping-resistor [No resistor in MHz operation] (Option) - Built in resonance capacitor at kHz version OSC1 I C1 Rf C2 - C1=C2 = 100pF [C1,C2 are not available for MHz version] 15% 1-6 Chapter 1. GMS36XXX Port Operation Value of X-reg 0 or 1 Value of Y-reg 0~ 7 SO : D(Y) RO : D(Y) Operation a 1 (High-Z) a0 a a 0 or 1 8 REMOUT port repeats `'L'' and `'H'' in pulse frequency. (when PMR = 5, it is fixed at `'L'' ) SO : REMOUT (PMR) 0 RO : REMOUT (PMR) 1 (High-Z) SO : D0 ~ D9 RO : D0 ~ D9 0 or 1 9 0 or 1 0 or 1 0 or 1 2 or 3 2 or 3 A~D E F 0 1 a 1 (High-Z) a0 SO : R(Y-Ah) a 1 RO : R(Y-Ah) a 0 SO : R0 ~ R3 a 1 RO : R0 ~ R3 a 0 SO : D0 ~ D9 a 1 (High-Z), R0 ~ R3 a 1 RO : D0 ~ D9 a 0, R0 ~ R3 a 0 SO : D(8) a 1 (High-Z) RO : D(8) a 0 SO : D(9) a 1 (High-Z) RO : D(9) a 0 Optional Features The GMS36XXX series offer the following optional features. Theses options are masked. * * * I/O terminals having pull-up resistor : R0 ~ R3 Input terminals having STOP release mode : K0 ~ K3, R0 ~ R3. Output form at STOP mode D0 ~ D9 : `'L'' or keep before stop mode. Theses options are offered default. * * Ceramic oscillation circuit contained (or not contained) [ This option is not available for MHz Ceramic oscillator. ] Instruction cycle selection : T = 48 / fOSC or 6 / fOSC 1-7 Chapter 1. GMS36XXX Electrical Characteristics Absolute maximum ratings (Ta = 25I) Parameter Supply Voltage Power dissipation Storage temperature range Input voltage Output voltage Symbol VDD PD Tstg VIN VOUT Max. rating -0.3 ~ 5.0 700 * -55 ~ 125 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3 Unit V mW I V V * Thermal derating above 25I : 6mW per degree I rise in temperature. Recommended operating condition Parameter Supply Voltage Operating temperature Symbol VDD Topr Condition 300KHz ~ 4MHz - Rating 2.0 ~ 3.6 -20 ~ +70 Unit I V 1-8 Chapter 1. GMS36XXX Electrical characteristics (Ta=25I, VDD= 3V) Limits Min. Input H current Input L current K Pull-up Resistance R Pull-up Resistance Feedback Resistance K, R Input H voltage K, R Input L voltage D, R Output L voltage OSC2 Output L voltage OSC2 Output H voltage REMOUT Output L current REMOUT leakage current D, R Output leakage current Current on STOP mode Operating Supply current 1 Operating Supply current 2 System colck frequency *1 Refer to *2 Refer to Parameter Symbol IIH IIL RPU1 RPU2 RFD VIH1 VIL1 VOL2*1 VOL3 VOH3 IOL1*2 IOLK1 IOLK2 ISTP IDD1*3 IDD2*3 fOSC fOSC -1 70 70 0.3 2.1 2.1 170 300 2.4 Unit Max. 1 300 300 3.0 0.9 0.4 0.9 250 1 1 1 1.0 1.5 1000 4 uA uA Condition Typ. 140 140 1.0 0.15 0.4 2.5 210 0.2 0.5 - VI = VDD , R having no Pull-up VI = GND, R having no Pull-up VI = GND VI = GND, Output off VOSC1= GND, VOSC2= GND IOL2 = 3mA IOL3 = 40uA (kHz) , 150uA(MHz) IOH3= -40uA (kHz), -150uA(MHz) VOL1= 0.3V VOUT= VDD, Output off VOUT= VDD, Output off At STOP mode fOSC= 455kHz fOSC= 4MHz kHz Version MHz Version. I I V V V V V mA uA uA uA mA mA kHz MHz fOSC/6 fOSC /48 Fig.1-5 Fig.1-6 IOL2 vs. VOL2 Graph IOL1 vs. VOL1 Graph *3 IDD1, IDD2, is measured at RESET mode. 1-9 Chapter 1. GMS36XXX A I Fig 1-5. IOL2 vs. VOL2 Graph. ( D, R Port ) h ] \ [[[ d [[ c [[ b [[ nnh^Y[ nnh^Ya tzw\ l a [[ [[ _ [[ ^ [[ ] [[ \ [[ [ [ Y[ [ Y_ [ Yc \ Y] \ Ya ] Y[ zw\ ] Y_ ] Yc ^ Y] ^ Ya _ Y[ nnh]Y[ Fig 1-6. IOL1 vs. VOL1 Graph. ( REMOUT port) 1-10 GMS36XXX GMS37XXX PACKAGE DIMENSIONS FUNCTIONAL DESCRIPTION INSTRUCTION APPLICATION GMS36XXXT GMS37XXXT EPROM 1 2 3 4 5 6 7 8 9 Chapter 2. GMS37XXX 2. GMS37XXX Description The GMS37XXX series are remote control transmitter which uses CMOS technology. This enables transmission code outputs of different configurations, multiple custom code output, and double push key output for easy fabrication. The GMS37XXX series are suitable for remote control of TV, VCR, FANS, Airconditioners, Audio Equipment, Toys, Games etc. It is possible to structure the 8 x 7 key matrix for GMS37112, and the 4 x 7 key matrix for GMS37004. Features * * * * * * * * * * * * * * Program memory : 1,024 bytes for GMS37004/112/140 Data memory : 32 4 bits 43 types of instruction set 3 levels of subroutine nesting Operating frequency : 300kHz ~ 1MHz at kHz version 2.4MHz ~ 4MHz at MHz version Instruction cycle : fOSC/6 at kHz version fOSC/48 at MHz version CMOS process (Single 3.0V power supply) Stop mode (Through internal instruction) Released stop mode by key input (Masked option) Built in Power-on Reset circuit Built in Low Voltage Detection circuit Built in capacitor for ceramic oscillation circuit at kHZ version Built in a watch dog timer (WDT) Low operating voltage : 2.0 ~ 3.6V (at 300kHz ~ 4MHz) O Table 2-1 GMS37XXX series members Series Program memory Data memory I/O ports Input ports Output ports Package GMS37004 1,024 32 GMS37112 1,024 32 GMS37140 1,024 32 O4 O4 O4 4 7 (D0~D6) 16DIP/SOP 4 4 7 (D0~D6) 20DIP/SOP/SSOP 4 4 10 (D0~D9) 24Skinny DIP/SOP 2-1 Chapter 2. GMS37XXX Block Diagram VDD GND 24 1 ROM 64word 8 4 8 4 Watchdog timer 10 Program counter 3-level Stack Power-on Reset Low-Voltage Detection O16page O8bit 10 4 08; Instruction Decoder 4 MUX 4 ALU 4 Control Signal 2 X-Reg RAM 16 16word x 2page x 4bit RAM Word Selector4 Y-Reg ACC ST 4 OSC R-Latch 10 D-Latch 4 Pulse Generator 10 4 4 4 2 3 6 OSC1 OSC2 7 8 9 K0 ~ K3 10 11 12 13 R0 ~ R3 14 15 16 17 18 19 20 D0 D1 D2 D3 D4 D5 D6 21 5 D7 D8 4 D9 22 NC 23 REMOUT * NC : No connection Fig 2-1 Block Diagram (In case of GMS37140) 2-2 Chapter 2. GMS37XXX Pin Assignment GND 1 OSC1 2 OSC2 3 K0 4 K1 5 K2 6 K3/Vpp 7 D0 8 16 VDD 15 REMOUT 14 D6 13 D5 12 D4 11 D3 10 D2 9 D1 GND 1 OSC1 2 OSC2 3 K0 4 K1 5 K2 6 K3/Vpp 7 R0 8 R1 9 R2 10 20 VDD 19 REMOUT 18 D6 17 D5 16 D4 15 D3 14 D2 13 D1 12 D0 11 R3 Fig 2-2 GMS37004 Pin Assignment (16DIP/SOP) Fig 2-3 GMS37112 Pin Assignment (20DIP/SOP/SSOP) GND 1 OSC1 2 OSC2 3 D9 4 D8 5 K0 6 K1 7 K2 8 K3/Vpp 9 R0 10 R1 11 R2 12 24 VDD 23 REMOUT 22 NC 21 D7 20 D6 19 D5 18 D4 17 D3 16 D2 15 D1 14 D0 13 R3 Fig 2-4 GMS37140 Pin Assignment (24Skinny-DIP/SOP) 2-3 Chapter 2. GMS37XXX Pin Description Pin VDD GND I/O - Function Connected to 2.0~ 3.6V power supply Connected to 0V power supply. K0 ~ K3 Input 4-bit input port with built in pull-up resistor. STOP mode is released by "L" input of each pin. ( masked option) D0 ~ D9 Output Each can be set and reset independently. The output is the structure of N-channel-open-drain. R0 ~ R3 I/O 4-bit I/O port. (Input mode is set only when each of them output "H".) In outputting, each can be set and reset independently(or at once.) The output is in the form of C-MOS. Pull-up resistor and STOP release mode can be respectively selected as masked option for each pin. (It is released by "L" input at STOP) Oscillator input. Input to the oscillator circuit and connection point for ceramic resonator. Internal capacitors available at kHz version. A feedback resistor is internally connected between this pin and OSC2. Connect a resonator between this pin and OSC1. High current output port. The output is in the form of CMOS. The state of large current on is "H". OSC1 Input OSC2 REMOUT Output Output 2-4 Chapter 2. GMS37XXX Pin Circuit Pin I/O I/O circuit pull-up Note - CMOS output. - "H" output at reset. (Option) - Built in MOS Tr for pull-up, about 140I. R0 ~ R3 I/O pull-up K0 ~ K3 I - Built in MOS Tr for pull-up, about 140I. D0 ~ D9 O - Open drain output. - "L" output at reset. REMOUT O - CMOS output. - "L" output at reset. - High current output source. 2-5 Chapter 2. GMS37XXX Pin I/O STOP I/O circuit Note OSC2 O OSC1 Rd - Built in feedbackresistor about 1 OSC2 - Built in damping-resistor [No resistor in MHz operation] (Option) - Built in resonance capacitor at kHz version OSC1 I C1 Rf C2 - C1=C2 = 100pF [C1,C2 are not available for MHz version] 15% 2-6 Chapter 2. GMS37XXX Port operation Value of X-reg 0 or 1 Value of Y-reg 0~ 7 SO : D(Y) RO : D(Y) Operation a 1 (High-Z) a0 a a 0 or 1 8 REMOUT port repeats `'H'' and `'L'' in pulse frequency. (when PMR = 5, it is fixed at `'H'' ) SO : REMOUT (PMR) 1 RO : REMOUT (PMR) 0 0 or 1 9 0 or 1 0 or 1 0 or 1 2 or 3 2 or 3 A~ D E F 0 1 a 1 (High-Z) a0 SO : R(Y-Ah) a 1 RO : R(Y-Ah) a 0 SO : R0 ~ R3 a 1 RO : R0 ~ R3 a 0 SO : D0 ~ D9 a 1 (High-Z), R0 ~ R3 a 1 RO : D0 ~ D9 a 0, R0 ~ R3 a 0 SO : D(8) a 1 (High-Z) RO : D(8) a 0 SO : D(9) a 1 (High-Z) RO : D(9) a 0 SO : D0 ~ D9 RO : D0 ~ D9 Optional Features The GMS37XXX series offer the following optional features. Theses options are masked. * * * I/O terminals having pull-up resistor : R0 ~ R3 Input terminals having STOP release mode : K0 ~ K3, R0 ~ R3. Output form at STOP mode D0 ~ D9 : `'L'' or keep before stop mode. Theses options are offered default. * * Ceramic oscillation circuit contained (or not contained) [ This option is not available for MHz Ceramic oscillator. ] Instruction cycle selection : T = 48 / fOSC or 6 / fOSC 2-7 Chapter 2. GMS37XXX Electrical Characteristics Absolute maximum ratings (Ta = 25I) Parameter Supply Voltage Power dissipation Storage temperature range Input voltage Output voltage Symbol VDD PD Tstg VIN VOUT Max. rating -0.3 ~ 5.0 700 * -55 ~ 125 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3 Unit V mW I V V * Thermal derating above 25I : 6mW per degree I rise in temperature. Recommended operating condition Parameter Supply Voltage Operating temperature Symbol VDD Topr Condition 300KHz ~ 4MHz - Rating 2.0 ~ 3.6 -20 ~ +70 Unit I V 2-8 Chapter 2. GMS37XXX Electrical characteristics (Ta=25I, VDD= 3V) Limits Min. Input H current Input L current K Pull-up Resistance R Pull-up Resistance Feedback Resistance K, R Input H voltage K, R Input L voltage D, R Output L voltage OSC2 Output L voltage OSC2 Output H voltage REMOUT Output L current REMOUT Output H current D, R Output leakage current Current on STOP mode Operating Supply current 1 Operating Supply current 2 System colck frequency *1 Refer to Parameter Symbol IIH IIL RPU1 RPU2 RFD VIH1 VIL1 VOL2*1 VOL3 VOH3 IOL1*2 IOH1*3 IOLK2 ISTP IDD1*3 IDD2*3 fOSC fOSC -1 70 70 0.3 2.1 2.1 1 -5 300 2.4 Unit Max. 1 300 300 3.0 0.9 0.4 0.9 4 -30 1 1 1.0 1.5 1000 4 uA uA Condition Typ. 140 140 1.0 0.15 0.4 2.5 2.2 -15 0.2 0.5 - VI = VDD , R having no Pull-up VI = GND, R having no Pull-up VI = GND VI = GND, Output off VOSC1= GND, VOSC2= GND IOL2 = 3mA IOL3 = 40uA (kHz), 150uA (MHz) IOH3= -40uA (kHz), -150uA (MHz) VOL1= 0.4V VOH1= 2V VOUT= VDD, Output off At STOP mode fOSC= 455kHz fOSC= 4MHz kHz Version MHz Version. I I V V V V V mA mA uA uA mA mA kHz MHz fOSC/6 fOSC /48 Fig.2-5 Fig.2-6 *3 Refer to Fig.2-7 *2 Refer to IOL2 vs. VOL2 Graph IOL1 vs. VOL1 Graph IOH1 vs. VOH1 Graph *4 IDD1, IDD2, is measured at RESET mode. 2-9 Chapter 2. GMS37XXX I |A} |} Fig 2-5. IOL2 vs. VOL2 Graph. ( D, R Port ) h ] c b a tzw\ l _ ^ ] \ [ [Y[ [Y_ [Yc \Y] \Ya ]Y[ ]Y_ zw\ ]Yc ^Y] ^Ya _Y[ nnh]Y[ nnh^Y[ nnh^Ya Fig 2-6. IOL1 vs VOL1 Graph (REMOUT Port) 2-10 Chapter 2. GMS37XXX h ] [ X X\[ tzs\ l X\ X][ X] X^[ X^ [Y[ [Y_ [Yc \Y] \Ya nnh^Ya nnh^Y[ nnh]Y[ ]Y[ ]Y_ zs\ ]Yc ^Y] ^Ya _Y[ Fig 2-7. IOH1 vs VOH1 Graph (REMOUT Port) 2-11 GMS36XXX GMS37XXX PACKAGE DIMENSIONS FUNCTIONAL DESCRIPTION INSTRUCTION APPLICATION GMS36XXXT GMS37XXXT EPROM 1 2 3 4 5 6 7 8 9 Chapter 3. PACKAGE DIMENSIONS 3. PACKAGE DIMENSIONS The GMS36/37XXX series can be used the following package dimesions. UNIT : INCH Fig 3-1. 16PDIP (300MIL) UNIT : INCH Fig 3-2. 16SOP (150MIL) (* This type is not supported at OTP) 3-1 Chapter 3. PACKAGE DIMENSIONS UNIT : INCH Fig 3-3. 16SOP (300MIL) UNIT : INCH Fig 3-4. 20SSOP (150MIL) 3-2 Chapter 3. PACKAGE DIMENSIONS UNIT : INCH Fig 3-5. 20PDIP (300MIL) UNIT : INCH Fig 3-6. 20SOP (300MIL) 3-3 Chapter 3. PACKAGE DIMENSIONS UNIT : INCH Fig 3-7. 24Skinny-DIP (300MIL) UNIT : INCH Fig 3-8. 24SOP (300MIL) 3-4 GMS36XXX GMS37XXX PACKAGE DIMENSIONS FUNCTIONAL DESCRIPTION INSTRUCTION APPLICATION GMS36XXXT GMS37XXXT EPROM 1 2 3 4 5 6 7 8 9 Chapter 4. FUNCTIONAL DESCRIPTION 4. FUNCTIONAL DESCRIPTION Program Memory (ROM) The GMS36/37XXX series can incorporate maximum 1,024 words (64 wordsO16 pagesO8bits) for program memory. Program counter PC (A0~A5) and page address register (A6~A9) are used to address the whole area of program memory having an instruction (8bits) to be next executed. The program memory consists of 64 words on each page, and thus each page can hold up to 64 steps of instructions. The program memory is composed as shown below. Program capacity (pages) 01 23 45 8 67 Page 0 6 63 Page 1 Page 2 Page 15 0 A0~A5 Program counter (PC) 6 Stack 1 2 15 A6~A9 Page address register (PA) 4 register (Level "1") (Level "2") 4 Page buffer (PB) (SR) (PSR) (Level "3") Fig 4-1 Configuration of Program Memory 4-1 Chapter 4. FUNCTIONAL DESCRIPTION ROM Address Register The following registers are used to address the ROM. * Page address register (PA) : Holds ROM's page number (0 ~ Fh) to be addressed. * Page buffer register (PB) : Value of PB is loaded by an LPBI command when newly addressing a page. Then it is shifted into the PA when rightly executing a branch instruction (BR) and a subroutine call (CAL). * Program counter (PC) : Available for addressing word on each page. * Stack register (SR) : Stores returned-word address in the subroutine call mode. (1) Page address register and page buffer register : Address one of pages #0 to #15 in the ROM by the 4-bit binary counter. Unlike the program counter, the page address register is usually unchanged so that the program will repeat on the same page unless a page changing command is issued. To change the page address, take two steps such as (1) writing in the page buffer what page to jump (execution of LPBI) and (2) execution of BR or CAL, because instruction code is of eight bits so that page and word can not be specified at the same time. In case a return instruction (RTN) is executed within the subroutine that has been called in the other page, the page address will be changed at the same time. (2) Program counter : This 6-bit binary counter increments for each fetch to address a word in the currently addressed page having an instruction to be next executed. For easier programming, at turning on the power, the program counter is reset to the zero location. The PA is also set to "0". Then the program counter specifies the next ROM address in random sequence. When BR, CAL or RTN instructions are decoded, the switches on each step are turned off not to update the address. Then, for BR or CAL, address data are taken in from the instruction operands (a0 to a5), or for RTN, and address is fetched from stack register No. 1. (3) Stack register : This stack register provides two stages each for the program counter (6bits) and the page address register (4bits) so that subroutine nesting can be made on two levels. 4-2 Chapter 4. FUNCTIONAL DESCRIPTION Data Memory (RAM) Up to 32 nibbles (16 words 2pages 4bits) is incorporated for storing data. The whole data memory area is indirectly specified by a data pointer (X,Y). Page number is specified by zero bit of X register, and words in the page by 4 bits in Y-register. Data memory is composed in 16 nibbles/page. Figure 2-2 shows the configuration. O O D0 D9 R0 R3 REMOUT Data memory page (0~1) Output port 0 1 2 3 Page 0 Page 1 15 4 a0~a3 0 1 Y-register (Y) X-register (X) Fig 4-2 Composition of Data Memory X-register (X) X-register is consist of 2bit, X0 is a data pointer of page in the RAM, X1 is only used for selecting of D8 ~ D9 with value of Y-register X1=0 Y=0 Y=1 D0 D1 X1=1 D8 D9 Table 4-1 Mapping table between X and Y register 4-3 Chapter 4. FUNCTIONAL DESCRIPTION Y-register (Y) Y-register has 4 bits. It operates as a data pointer or a general-purpose register. Y-register specifies an address (a0~a3) in a page of data memory, as well as it is used to specify an output port. Further it is used to specify a mode of carrier signal outputted from the REMOUT port. It can also be treated as a generalpurpose register on a program. Accumulator (ACC) The 4-bit register for holding data and calculation results. Arithmetic and Logic Unit (ALU) In this unit, 4bits of adder/comparator are connected in parallel as it's main components and they are combined with status latch and status logic (flag.) (1) Operation circuit (ALU) : The adder/comparator serves fundamentally for full addition and data comparison. It executes subtraction by making a complement by processing an inversed output of ACC (ACC+1) (2) Status logic : This is to bring an ST, or flag to control the flow of a program. It occurs when a specified instruction is executed in three cases such as overflow or underflow in operation and two inputs unequal. 4-4 Chapter 4. FUNCTIONAL DESCRIPTION State Counter (SC) A fundamental machine cycle timing chart is shown below. Every instruction is one byte length. Its execution time is the same. Execution of one instruction takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total). Virtually these two cycles proceed simultaneously, and thus it is apparently completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN instructions is normal execution time since they change an addressing sequentially. Therefore, the next instruction is prefetched so that its execution is completed within the fetch cycle. T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6 Fetch cycle N Execute cycle N-1 Execute cycle N Fetch cycle N-1 Phasee Phasee Phasee Machine Cycle Machine Cycle Fig. 4-3 Fundamental timing chart 4-5 Chapter 4. FUNCTIONAL DESCRIPTION Clock Generator The GMS36/37XXX series has an internal clock oscillator. The oscillator circuit is designed to operate with an external ceramic resonator. Internal capacitors are available at kHz version. Oscillator circuit is able to organize by connecting ceramic resonator to outside. * It is necessary to connect capacitor to outside in order to change ceramic resonator, you must refer to a manufacturers resonator matching guide. OSC1 OSC2 2 C1 3 C2 rx~^aZ^b\\]v _]ds _^]s _s _c[s [[s a_[s x}ll n~m_]d{ X n~m_p n~m_c[p n~m[[p n~ma_[{ n| X m_^] m_ m_c[ m[[ ma_[ w Y n\hn]hz n\hn]hz n\hn]hz n\hn]hz n\hn]hz n\hn]hz rx~^aZ^b\\]x ov v znp}l x}ll x}ll n| nz}ppns ^Ya_xs qn}^Ya_x~n vm}X^Ya_xvp n~~[^a_xr[a n~nn^Ya_xr[sa ^Ya_xr n}^Ya_x~ ^Yc_xs qn}^Ya_x~n vm}X^Yc_xvp n~~[^c_xr[a n~nn^Yc_xr[sa ^Yc_xr n}^Yc_x~ _Y[[xs qn}_Y[x~n vm}X_Y[[xvp n~~[_[[xr[^ n~nn_Y[[xr _Y[[xr n}_Y[[x~ * All type have the built-in loading capacitors. 4-1 Chapter 4. FUNCTIONAL DESCRIPTION Pulse Generator The following frequency and duty ratio are selected for carrier signal outputted from the REMOUT port depending on a PMR (Pulse Mode Register) value set in a program. T T1 PMR 0 1 2 3 4 5 6 7 REMOUT signal T=1/fPUL = 12/fOSC [96/fOSC], T=1/fPUL = 12/fOSC [96/fOSC], T=1/fPUL = 8/fOSC [64/fOSC], T=1/fPUL = 8/fOSC [64/fOSC], T=1/fPUL = 11/fOSC [88/fOSC], No Pulse (same to D0 ~ D9) T=1/fPUL = 12/fOSC [96/fOSC], No pulse (same to D0 ~ D9) T1/T = 1/4 T1/T = 1/2 T1/T = 1/3 T1/T = 1/2 T1/T = 1/4 T1/T = 4/11 * Default value is "0" * [ ] means the value of "T", when Instruction cycle is fOSC/48 in MHz version Table 4-2 PMR selection table 4-7 Chapter 4. FUNCTIONAL DESCRIPTION Reset Operation GMS36/37XXX has three reset sources. One is a built-in Power-on reset circuit, another is a built-in Low VDD Detection circuit, the other is the overflow of Watch Dog Timer. (WDT) All reset operations are internal in the GMS36/37XXX. Built-in Power On Reset Circuit GMS36/37XXX has a built-in Power-on reset circuit consisting of an about 1 Resistor and a 3pF Capacitor. When the Power-on reset pulse occurs, system reset signal is latched and WDT is cleared. After the overflow time of WDT (213 x System clock time) system reset signal is released. 9'' &RXQWHU :'7 6\VWHP 5(6(7% S) *1' VCC System RESETB treset About 108msec at fosc = 455kHz Fig. 4-4 Power-On Reset Circuit and Timing Chart 4-8 Chapter 4. FUNCTIONAL DESCRIPTION Built-in Low VDD Detection Circuit GMS36/37XXX has a Low VDD detection circuit. If VDD become Reset Voltage of Low VDD Detection circuit at active status, system reset occur and WDT is cleared. After VDD is increased upper Reset Voltage again, WDT is re-counted and if WDT is overflowed, system reset is released. VDD Reset Voltage Internal RESETB About 108msec at fosc =455kHz Fig. 4-5 Low Voltage Detection diagram ^Y[ ]Yc ]Ya ]Y_ ]Y] ]Y[ ST \Yc \Ya \Y_ \Y] \Y[ [Yc [Ya [Y_ [Y] [Y[ X] [ X\ [ [ xY z n{ W }zx w o \[ ][ ^[ _[ [ a[ b[ ST Fig. 4-6 Low Voltage vs Temperature 4-9 Chapter 4. FUNCTIONAL DESCRIPTION Watch Dog Timer (WDT) Watch dog timer is organized binary of 14 steps. The signal of fOSC/6 cycle comes in the first step of WDT after WDT reset. If this counter was overflowed, reset signal automatically come out so that internal circuit is initialized. The overflow time is 6O2 13/fOSC (108.026ms at fOSC=455KHz.) 8O6O213/fOSC (108.026ms at fOSC = 3.64MHz) Normally, the binary counter must be reset before the overflow by using reset instruction (WDTR), Power-on reset pulse or Low VDD detection pulse. * It is constantly reset in STOP mode. When STOP is released, counting is restarted. fOSC/6 or fOSC/48 Binary counter(14 steps) RESET (edge-trigger) CPU reset Reset by instruction Power-On Reset Low VDD Detection Fig. 4-7 Block Diagram of Watch-dog Timer 4-10 Chapter 4. FUNCTIONAL DESCRIPTION STOP Operation Stop mode can be achieved by STOP instructions. In stop mode : 1. Oscillator is stopped, the operating current is low. 2. Watch dog timer is reset, REMOUT output is disable (High-Z at GMS36XXX(T) , "L" at GMS37XXX(T)) 3. Part other than WDT and REMOUT output have a value before come into stop mode. * But the state of D0 ~ D9 output in stop mode is able to choose as masked option. "L" output or same level before come into stop mode. The Function to release stop mode is able to choose each bit of K or R input as masked option. Stop mode is released when one of K or R input is going to "L". 1. State of D0 ~ D9 output and REMOUT output is return to state of before stop mode is achieved. 2. After 210 O{System clock time} for stable oscillating, first instruction start to operate. 3. In return to normal operation, WDT is counted from zero again. But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction is same to NOP instruction. 4-11 GMS36XXX GMS37XXX PACKAGE DIMENSIONS FUNCTIONAL DESCRIPTION INSTRUCTION APPLICATION GMS36XXXT GMS37XXXT EPROM 1 2 3 4 5 6 7 8 9 Chapter 5. INSTRUCTION CHAPTER 5. INSTRUCTION INSTRUCTION FORMAT All of the 43 instruction in GMS36/37XXX(T) series is format in two fields of OP code and operand which consist of eight bits. The following formats are available with different types of operands. *Formate All eight bits are for OP code without operand. *Formate Two bits are for operand and six bits for OP code. Two bits of operand are used for specifying bits of RAM and X-register (bit 1 and bit 7 are fixed at I0I) *Formate Four bits are for operand and the others are OP code. Four bits of operand are used for specifying a constant loaded in RAM or Yregister, a comparison value of compare command, or page addressing in ROM. *Format i Six bits are for operand and the others are OP code. Six bits of operand are used for word addressing in the ROM. 5-1 Chapter 5. INSTRUCTION INSTRUCTION TABLE The GMS36/37XXX(T) series provides the following 43 basic instructions. Category 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Arithmetic ROM Address RAM Bit Manipulation Immediate RAM to Register Register to Register Mnemonic LAY LYA LAZ LMA LMAIY LYM LAM XMA LYI i LMIIY i LXI n SEM n REM n TM n BR a CAL a RTN LPBI i AM SM IM DM IA IY DA Function ST*1 S S S S S S S S S S S S S E S S S S C B C B S C B aY YaA Aa0 A M(X,Y) aA M(X,Y) a A, Y a Y+1 Y a M(X,Y) A a M(X,Y) A a M(X,Y) Yai M(X,Y) a i, Y a Y+1 Xan M(n) a 1 M(n) a 0 TEST M(n) = 1 if ST = 1 then Branch if ST = 1 then Subroutine call Return from Subroutine ai A a A + M(X,Y) A a M(X,Y) - A A a M(X,Y) + 1 A a M(X,Y) - 1 A a A+1 Y a Y+1 A a A-1 PB 5-2 Chapter 5. INSTRUCTION Category 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Control 42 43 Input / Output Comparison Arithmetic Mnemonic DY EORM NEGA ALEM ALEI i MNEZ YNEA YNEI i KNEZ RNEZ LAK LAR SO RO WDTR STOP LPY NOP Y Function ST*1 B S Z E E N N N N N S S S S S S S S a Y-1 A a A + M (X,Y) A a A+1 TEST A o M(X,Y) TEST A o i TEST M(X,Y) o 0 TEST Y o A TEST Y o i TEST K o 0 TEST R o 0 AaK AaR Outputa 0 at GMS36XXX, 1 at GMS37XXX Outputa 1 at GMS36XXX, 0 at GMS37XXX Watch Dog Timer Reset Stop operation PMR aY No operation Note) i = 0~f, n = 0~3, a = 6bit PC Address *1 Column ST indicates conditions for changing status. Symbols have the following meanings S : On executing an instruction, status is unconditionally set. C : Status is only set when carry or borrow has occurred in operation. B : Status is only set when borrow has not occurred in operation. E : Status is only set when equality is found in comparison. N : Status is only set when equality is not found in comparison. Z : Status is only set when the result is zero. 5-3 Chapter 5. INSTRUCTION DETAILS OF INSTRUCTION SYSTEM All 43 basic instructions of the GMS36/37XXX(T) Series are one by one described in detail below. Description Form Each instruction is headlined with its mnemonic symbol according to the instructions table given earlier. Then, for quick reference, it is described with basic items as shown below. After that, detailed comment follows. * Items : - Naming : - Status : - Format : - Operand : - Function Full spelling of mnemonic symbol Check of status function Categorized into to Omitted for Format ei e 5-4 Chapter 5. INSTRUCTION (1) LAY Naming : Status : Format : Function : Load Accumulator from Y-Register Set I AaY Data of four bits in the Y-register is unconditionally transferred to the accumulator. Data in the Y-register is left unchanged. (2) LYA Naming : Status : Format : Function : Load Y-register from Accumulator Set I YaA Load Y-register from Accumulator Clear Accumulator Set I Aa0 Data in the accumulator is unconditionally reset to zero. Load Memory from Accumulator Set I M(X,Y) a A Data of four bits from the accumulator is stored in the RAM location addressed by the X-register and Y-register. Such data is left unchanged. (5) LMAIY Naming : Status : Format : Function : Load Memory from Accumulator and Increment Y-Register Set I M(X,Y) a A, Y a Y+1 Data of four bits from the accumulator is stored in the RAM location addressed by the X-register and Y-register. Such data is left unchanged. 5-5 Chapter 5. INSTRUCTION (6) LYM Naming : Status : Format : Function : Load Y-Register form Memory Set I Y a M(X,Y) Data from the RAM location addressed by the X-register and Y-register is loaded into the Y-register. Data in the memory is left unchanged. (7) LAM Naming : Status : Format : Function : Load Accumulator from Memory Set I A a M(X,Y) Data from the RAM location addressed by the X-register and Y-register is loaded into the Y-register. Data in the memory is left unchanged. (8) XMA Naming : Status : Format : Function : Exchanged Memory and Accumulator Set I M(X,Y) a A Data from the memory addressed by X-register and Y-register is exchanged with data from the accumulator. For example, this instruction is useful to fetch a memory word into the accumulator for operation and store current data from the accumulator into the RAM. The accumulator can be restored by another XMA instruction. (9) LYI i Naming : Status : Format : Operand : Function : Load Y-Register from Immediate Set Constant 0 o i o 15 Yai To load a constant in Y-register. It is typically used to specify Y-register in a particular RAM word address, to specify the address of a selected output line, to set Y-register for specifying a carrier signal outputted from OUT port, and to initialize Y-register for loop control. The accumulator can be restored by another XMA instruction. Data of four bits from operand of instruction is transferred to the Y-register. e 5-6 Chapter 5. INSTRUCTION (10) LMIIY i Naming : Status : Format : Operand : Function : Load Memory from Immediate and Increment Y-Register Set Constant 0 o i o 15 M(X,Y) a i, Y a Y + 1 Data of four bits from operand of instruction is stored into the RAM location addressed by the X-register and Y-register. Then data in the Y-register is incremented by one. e (11) LXI n Naming : Status : Format : Operand : Function : Load X-Register from Immediate Set X file address 0 o n o 3 Xan A constant is loaded in X-register. It is used to set X-register in an index of desired RAM page. Operand of 1 bit of command is loaded in X-register. e (12) SEM n Naming : Status : Format : Operand : Function : Set Memory Bit Set Bit address 0 o n o 3 M(X,Y,n) a 1 Depending on the selection in operand of operand, one of four bits is set as logic 1 in the RAM memory addressed in accordance with the data of the X-register and Y-register. e (13) REM n Naming : Status : Format : Operand : Function : Reset Memory Bit Set Bit address 0 o n o 3 M(X,Y,n) a 0 Depending on the selection in operand of operand, one of four bits is set as logic 0 in the RAM memory addressed in accordance with the data of the X-register and Y-register. e 5-7 Chapter 5. INSTRUCTION (14) TM n Naming : Status : Format : Operand : Function : Test Memory Bit Comparison results to status Bit address 0 o n o 3 M(X,Y,n) a 1? ST a 1 when M(X,Y,n)=1, ST a 0 when M(X,Y,n)=0 A test is made to find if the selected memory bit is logic. 1 Status is set depending on the result. e (15) BR a Naming : Status : Format : Operand : Function : Branch on status 1 Conditional depending on the status i Branch address a (Addr) When ST =1 , PA a PB, PC a a(Addr) When ST = 0, PC a PC + 1, ST a 1 Note : PC indicates the next address in a fixed sequence that is actually pseudo-random count. For some programs, normal sequential program execution can be change. A branch is conditionally implemented depending on the status of results obtained by executing the previous instruction. * Branch instruction is always conditional depending on the status. a. If the status is reset (logic 0), a branch instruction is not rightly executed but the next instruction of the sequence is executed. b. If the status is set (logic 1), a branch instruction is executed as follows. * Branch is available in two types - short and long. The former is for addressing in the current page and the latter for addressing in the other page. Which type of branch to exeute is decided according to the PB register. To execute a long branch, data of the PB register should in advance be modified to a desired page address through the LPBI instruction. 5-8 Chapter 5. INSTRUCTION (16) CAL a Naming : Status : Format : Operand : Function : Subroutine Call on status 1 Conditional depending on the status i Subroutine code address a(Addr) When ST =1 , PC a a(Addr) PA a PB SR1 a PC + 1, PSR1 a PA SR2 a SR1 PSR2 a PSR1 SR3 a SR2 PSR3 a PSR2 When ST = 0 PC a PC + 1 PB a PS ST a 1 Note : PC actually has pseudo-random count against the next instruction. * In a program, control is allowed to be transferred to a mutual subroutine. Since a call instruction preserves the return address, it is possible to call the subroutine from different locations in a program, and the subroutine can return control accurately to the address that is preserved by the use of the call return instruction (RTN). Such calling is always conditional depending on the status. a. If the status is reset, call is not executed. b. If the status is set, call is rightly executed. The subroutine stack (SR) of three levels enables a subroutine to be manipulated on three levels. Besides, a long call (to call another page) can be executed on any level. * For a long call, an LPBI instruction should be executed before the CAL. When LPBI is omitted (and when PA=PB), a short call (calling in the same page) is executed. 5-9 Chapter 5. INSTRUCTION (17) RTN Naming : Status : Format : Function : Return from Subroutine Set PA, PB a PSR1 PSR1 a PSR2 PSR2 a PSR3 PSR3 a PSR2 a1 ST Control is returned from the called subroutine to the calling program. Control is returned to its home routine by transferring to the PC the data of the return address that has been saved in the stack register (SR1). At the same time, data of the page stack register (PSR1) is transferred to the PA and PB. e PC a SR1 SR1 a SR2 SR2 a SR3 SR3 a SR3 (18) LPBI i Naming : Status : Format : Operand : Function : Load Page Buffer Register from Immediate Set ROM page address 0 o i o 15 PB a i A new ROM page address is loaded into the page buffer register (PB). This loading is necessary for a long branch or call instruction. The PB register is loaded together with three bits from 4 bit operand. e (19) AM Naming : Status : Format : Function : Add Accumulator to Memory and Status 1 on Carry Carry to status A a M(X,Y)+A, ST a 1(when total>15), ST a 0 (when total o15) Data in the memory location addressed by the X and Y-register is added to data of the accumulator. Results are stored in the accumulator. Carry data as results is transferred to status. When the total is more than 15, a carry is caused to put I1I in the status. Data in the memory is not changed. e 5-10 Chapter 5. INSTRUCTION (20) SM Naming : Status : Format : Function : ST a 1(when A o M(X,Y)) ST a 0(when A > M(X,Y)) e Subtract Accumulator to Memory and Status 1 Not Borrow Carry to status A a M(X,Y) - A (21) IM Naming : Status : Format : Function : Increment Memory and Status 1 on Carry Carry to status ST a 1(when M(X,Y) o 15) ST a 0(when M(X,Y) < 15) e A a M(X,Y) + 1 (22) DM Naming : Status : Format : Function : Decrement Memory and Status 1 on Not Borrow Carry to status ST a 1(when M(X,Y) o1) ST a 0 (when M(X,Y) = 0) Data of the memory addressed by the X and Y-register is fetched, and one is subtracted from this word (addition of Fh)> Results are stored in the accumulator. Carry data as results is transferred to the status. If the data is more than or equal to one, the status is set to indicate that no borrow is caused. The memory is left unchanged. e A a M(X,Y) - 1 5-11 Chapter 5. INSTRUCTION (23) IA Naming : Status : Format : Function : Increment Accumulator Set A a A+1 Data of the accumulator is incremented by one. Results are returned to the accumulator. A carry is not allowed to have effect upon the status. e (24) IY Naming : Status : Format : Function : Increment Y-Register and Status 1 on Carry Carry to status ST a 1 (when Y = 15) ST a 0 (when Y < 15) Data of the Y-register is incremented by one and results are returned to the Y-register. Carry data as results is transferred to the status. When the total is more than 15, the status is set. e Y a Y+1 (25) DA Naming : Status : Format : Function : ST a 1(when A o1) ST a 0 (when A = 0) Data of the accumulator is decremented by one. As a result (by addition of Fh), if a borrow is caused, the status is reset to I0I by logic. If the data is more than one, no borrow occurs and thus the status is set to I1I. e Decrement Accumulator and Status 1 on Borrow Carry to status A a A -1 5-12 Chapter 5. INSTRUCTION (26) DY Naming : Status : Format : Function : Decrement Y-Register and Status 1 on Not Borrow Carry to status ST a 1 (when Y o 1) ST a 0 (when Y = 0) Data of the Y-register is decremented by one. Data of the Y-register is decremented by one by addition of minus 1 (Fh). Carry data as results is transferred to the status. When the results is equal to 15, the status is set to indicate that no borrow has not occurred. e Y a Y -1 (27) EORM Naming : Status : Format : Function : A a M(X,Y) + A Data of the accumulator is, through a Exclusive OR, subtracted from the memory word addressed by X and Yregister. Results are stored into the accumulator. e Exclusive or Memory and Accumulator Set (28) NEGA Naming : Status : Format : Function : ST a 1(when A = 0) ST a 0 (when A != 0) The 2s complement of a word in the accumulator is obtained. The 2s complement in the accumulator is calculated by adding one to the 1s complement in the accumulator. Results are stored into the accumulator. Carry data is transferred to the status. When data of the accumulator is zero, a carry is caused to set the status to I1I. e Negate Accumulator and Status 1 on Zero Carry to status A a A+1 5-13 Chapter 5. INSTRUCTION (29) ALEM Naming : Status : Format : Function : Accumulator Less Equal Memory Carry to status ST a 1 (when A o M(X,Y)) ST a 0 (when A > M(X,Y)) Data of the accumulator is, through a complemental addition, subtracted from data in the memory location addressed by the X and Y-register. Carry data obtained is transferred to the status. When the status is I1I, it indicates that the data of the accumulator is less than or equal to the data of the memory word. Neither of those data is not changed. e A o M(X,Y) (30) ALEI Naming : Status : Format : Function : Accumulator Less Equal Immediate Carry to status ST a 1 (when A o i) ST a 0 (when A > i) e A oi (31) MNEZ Naming : Status : Format : Function : Memory Not Equal Zero Comparison results to status ST a 1(when M(X,Y) o 0) ST a 0 (when M(X,Y) = 0) A memory word is compared with zero. Data in the memory addressed by the X and Y-register is logically compared with zero. Comparison data is thransferred to the status. Unless it is zero, the status is set. e M(X,Y) o 0 5-14 Chapter 5. INSTRUCTION (32) YNEA Naming : Status : Format : Function : Y-Register Not Equal Accumulator Comparison results to status ST a 1 (when Y o A) ST a 0 (when Y = A) Data of Y-register and accumulator are compared to check if they are not equal. Data of the Y-register and accumulator are logically compared. Results are transferred to the status. Unless they are equal, the status is set. e YoA (33) YNEI Naming : Status : Format : Operand : Function : Y-Register Not Equal Immediate Comparison results to status e ST a 1 (when Y o i) ST a 0 (when Y = i) The constant of the Y-register is logically compared with 4bit operand. Results are transferred to the status. Unless the operand is equal to the constant, the status is set. Constant 0 o i o 15 Yoi (34) KNEZ Naming : Status : Format : Function : K Not Equal Zero The status is set only when not equal When K o 0, ST a 1 A test is made to check if K is not zero. Data on K are compared with zero. Results are transferred to the status. For input data not equal to zero, the status is set. e (35) RNEZ Naming : Status : Format : Function : R Not Equal Zero The status is set only when not equal When R o 0, ST a 1 A test is made to check if R is not zero. Data on R are compared with zero. Results are transferred to the status. For input data not equal to zero, the status is set. e 5-15 Chapter 5. INSTRUCTION (36) LAK Naming : Status : Format : Function : Load Accumulator from K Set AaK Data on K are transferred to the accumulator e Load Accumulator from R Set AaR Data on R are transferred to the accumulator e (38) SO Naming : Status : Format : Function : Set Output Register Latch Set D(Y) a 1 0oYo7 REMOUT a 0(PMR=5) Y = 8 at GMS36XXX(T) REMOUT a 1(PMR=5) Y = 8 at GMS37XXX(T) D0~D9 a 1 (High-Z) Y=9 R(Y) a 1 Ah o Y o Dh Ra1 Y = Eh D0~D9, R a 1 Y = Fh A single D output line is set to logic 1, if data of Y-register is between 0 to 7. Carrier frequency come out from REMOUT port, if data of Y-register is 8. All D output line is set to logic 1, if data of Y-register is 9. It is no operation, if data of Y-register between 10 to 15. When Y is between Ah and Dh, one of R output lines is set at logic 1. When Y is Eh, the output of R is set at logic 1. When Y is Fh, the output D0~D9 and R are set at logic 1. Data of Y-register is between 0 to 7, selects appropriate D output. Data of Y-register is 8, selects REMOUT port. Data of Y-register is 9, selects all D port. Data in Y-register, when between Ah and Dh, selects an appropriate R output (R0~R3). Data in Y-register, when it is Eh, selects all of R0~R3. Data in Y-register, when it is Fh, selects all of D0~D9 and R0~R3. e 5-16 Chapter 5. INSTRUCTION (39) RO Naming : Status : Format : Function : Reset Output Register Latch Set D(Y) a 0 0oYo7 REMOUT a 1 Y = 8 at GMS36XXX(T) REMOUT a 0 Y = 8 at GMS37XXX(T) D0~D9 a 0 Y=9 R(Y) a 0 Ah o Y o Dh Ra0 Y = Eh D0~D9, R a 0 Y = Fh A single D output line is set to logic 0, if data of Y-register is between 0 to 9. REMOUT port is set to logic 0, if data of Y-register is 9. All D output line is set to logic 0, if data of Y-register is 9. When Y is between Ah and Dh, one of R output lines is set at logic 0. When Y is Eh, the output of R is set at logic 0 When Y is Fh, the output D0~D9 and R are set at logic 1. Data of Y-register is between 0 to 7, selects appropriate D output. Data of Y-register is 8, selects REMOUT port. Data of Y-register is 9, selects D port. Data in Y-register, when between Ah and Dh, selects an appropriate R output (R0~R3). Data in Y-register, when it is Eh, selects all of R0~R3. Data in Y-register, when it is Fh, selects all of D0~D9 and R0~R3. e (40) WDTR Naming : Status : Format : Function : Watch Dog Timer Reset Set e Reset Watch Dog Timer (WDT) Normally, you should reset this counter before overflowed counter for dc watch dog timer. this instruction controls this reset signal. 5-17 Chapter 5. INSTRUCTION (41) STOP Naming : Status : Format : Function : STOP Set e Operate the stop function Stopped oscillator, and little current. (See 1-12 page, STOP function.) (42) LPY Naming : Status : Format : Function : Pulse Mode Set Set PMR a Y Selects a pulse signal outputted from REMOUT port. e (43) NOP Naming : Status : Format : Function : No Operation Set e No operation 5-18 GMS36XXX GMS37XXX PACKAGE DIMENSIONS FUNCTIONAL DESCRIPTION INSTRUCTION APPLICATION GMS36XXXT GMS37XXXT EPROM 1 2 3 4 5 6 7 8 9 Chapter 6. Application Guideline for S/W 1. All rams need to be initialized to zero in reset address for proper design. 2. Make the output ports H after reset. 3. Do not use WDTR instruction in subroutine. 4. Before reading the input port the waiting time should be more than 200uS. 5. To decrease current consumption, make the output port as high in normal routine except for key scan strobe and STOP mode. 6. We recommend you do not use all 64 bytes in a page. You had better write BR $ in unused area. This will help you prevent unusual operation of MCU. 7. Be careful not to use long call or branch (CALL,BL) with arithmetic manipulation. If you want to use branch right after arithmetic manipulation, the long call or branch will be against your intention. ex) LAR ; The value of R ports -> Accumulator A :S=0 ALEI 14 ; Ao14 : S = 1, BL TRUE ; S is always 1 because BL is composed of LPBI and BR. -------------- Fail 14 LAR ; The value of R ports -> Accumulator ALEI 14 ; Ao14 : S = 1, A :S=0 BR TRUE ; When S is 1 Branch will occur. Otherwise Branch will not occur and LAK ; next instruction will be operated. -------------- Right 14 6-1 Chapter 6. Application *06 &LUFXLW 'LDJUDP . . . . 5 5 5 5 26& 26& *1' *065%;;; We recommend alkaline battery 9GG 5(0 287 ' ' ' ' ' ' 3*1' 6-2 Chapter 6. Application *06 &LUFXLW 'LDJUDP . . . *065&;;; 26& 26& *1' We recommend alkaline battery . 5 5 5 5 9GG 5(0 287 ' ' ' ' ' ' ' 6-3 Chapter 6. Application 7UXWK 7DEOH IRU H[DPSOH SURJUDP CUSTOM:04H vp yzY v[\ v[] v[^ v[_ v[ v[a v[b v[c v[d v\[ v\\ v\] v\^ v\_ v\ v\a v\b v\c v\d v][ v]\ v]] v]^ v]_ v] v]a v]b v]c ollSsT [[ [\ [] [^ [_ [ [a [b [c [d [l [m [n [o [p [q \[ \\ \] \^ \_ \ \a \b \c \d \l \m vp yzY v]d v^[ v^\ v^] v^^ v^_ v^ v^a v^b v^c v^d v_[ v_\ v_] v_^ v__ v_ v_a v_b v_c v_d v[ v\ v] v^ v_ v va ollSsT \n \o \p \q ][ ]\ ]] ]^ ]_ ] ]a ]b ]c ]d ]l ]m ]n ]o ]p ]q ^[ ^\ ^] ^^ ^_ ^ ^a ^b 6-4 Chapter 6. Application 2XWSXW ZDYHIRUP RI X3'* $ VLQJOH SXOVH PRGXODWHG ZLWK .+] VLJQDO DW .+] 7F &DUULHU IUHTXHQF\ I&$5 7F I26& 77F 7 'XW\ UDWLR - Configuration of Flame 1st flame Lead code 9ms Custom code Custom code Data code Data code 4.5ms C0 C1 C2 C3 C4 C5 C6 C7 C0 C1 C2 C3 C4 C5 C6 C7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D5 D7 - Repeat code 0.56ms 9ms 2.25ms - Bit Description Bit I0I 0.56ms Bit I1I 0.56ms 1.125ms 2.25ms - Flame Interval : Tf The transmitted waveform as long as a key is depressed Tf=108mS Tf=108mS 6-5 Chapter 6. Application Example program - uPD6121G (c) 1/41/2C AAEAAEA 1/2C IAAA AAEAAEA AAE 1/4 AAEAE 1/2C AAEAE | (c) (c) (c) | (c) (c) (c) (c) (c) | (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) | | | | | t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t | t t t t t t t t t t t t t t | t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t 1/2A |(c) tt ttttttttt ttt|t|tt|tt tt| tt tt|tttttttt| ttttttttt tt|t(R)t| tt ttt ttttttttt ttttttttt t|tt|t|t(c)||t(c) tt ttttttttt(c) tt ttttt tttttttttt tt ttttttttt(c) tt|ttttttt| tt|ttttttt ttttttttt ttttttt ttttttt tttttttt tt|tttttttt| tttttttt tt| t{t(c)t|tt(c)|(c) ttttttttt tt(R) tt|tttttttt ttttttttt(c) tttttttttt tt|tttttttt| ttttttttt tt|tttttttt tt tttttttt tt|tttttttt %/ . ( < 6-6 Chapter 6. Application t t t t t t t t t t t | t t t t t t t t t t t t t t t t t t t t t t t t t t t | t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t | t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t | | | | | t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t | | || | tttttt ttttt tt|ttttttttx ttttttttttttt ttttt|ttttttttx tttttttttttt ttttt ttttt| ttttttttttt ttttt ttttttttttt tttttttttttt ttttt| ttttttttttt tttttttttttt| tttttttttttt ttttt tt| |t| t t|tt | | | | | | (c) | (c) | | | 6-7 Chapter 6. Application t t t t t t t t t t t t t t t t t t t t t t t t t t t t tt tt tt tt t t t t | t tt t t tt t t t t t t t t t t t t t t t t t t t t tttttttttttt tttttttttttttttt tttttttttttttttttt(c)| t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t tt tt tt tt tt tt tt tt t t t t t t t t | t ttttttt(c) ttttttt| |tttttttt | | t t tt tt t t t t ttttx ttt tttx tttttttttt| ttttttttttt ttt|tttttttt ttt ttt|tttttttt tttttttttt tttttttttt tttttttttt| ttt tttttttttt tttt ttttttttt ttt|tttttttt ttttttttt ttt|tttttttt ttttttttt ttt|tttttttt tttttttt tt|tttttttt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t | | t | | | | | | | t t t t t t t t t t t t tt t t t t t t t t t t t t t t t t t t t t ttttttt ttttt ttttttttt ttttttt tt t tt t tt t tt t tt t tt t tt t tt tt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t tttttt tttttt tttttt tttttt tttttt tttttt 6-8 Chapter 6. Application t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t (c) t t t t (c) t t t t t t t t t t t t t t (c) t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t ttttttt tttttttt(c) t t t | t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t tt tt|tt tttt tt|tt ttt tt tt tt tt ttt tt ttt tttt ttt tt tt ttt tt|tt ttt tt tt ttt tttt tt|tt ttt tt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t x x t t | |tttttttt tttttttttt ttttttttttt| (c) (c) ttttttt ttttttttttt ttttttttttt tt ttttttttttt tttttttttt| ttttttttttt ttttttttttt tttttttttt tttttttttttt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t tt tt tt|tt tt| ttt tt tt tt tt tt(R) tt tt(R) tt|(R) tt tt tt tt|tt tttt tttt tttt tttt t tttt t t t t t t t t t t t t t t t t tt tt tt ttt tt t t t t t t t t tttttt tttttt (c)(c)t|(c)tt|ttt| t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t x 6-9 Chapter 6. Application t t t t ttt|ttttttttx ttttttttt tttttttttt ttt ttttttttt ttt| ttttttttt tttttttttt tttttttttttttttttt (c)tttttttttt tttttttttttttttttt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t AE AE t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t | t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t * 1/2 A | t | A | t | | t t t t tt tt tt tt tt tt tt tt tt tt tt tt tt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t (c) (c) (c) (c) (c) (c) (c) (c) t (c) (c) t t t t t t t t t t t t t t t t t t t t t t t t t t tttttt tttttttt t tt | tt tt tt t t tt t t t tt ttttt(c) t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t| t t t t t t t t (c) AtttttttAE ttttttt tttttttt| t t t tt tt tt t t t t t t t t t t t t tx t tx 6-10 Chapter 6. Application t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t | 6-11 Chapter 6. Application 5HIHUHQFH WR *06;;;7 %' $WWDFK UHVRQDWRU WR ; &RQQHFW EDVH DQG FROOHFWRU DW 4 &RQQHFW 3*1' DQG 75*1' ZLWK MXPSHU DW ( & % ( 4 5 5 5 ; ( ' 3*1' 75*1' $ ....5555 % ....5555 '6 & '6 5(0287 75287 26& ' *1' 6:a 6:a '''' '''' '''' '''' . . . . 5 5 5 5 ' ' ' ' ' ' '6 LV FRQQHFWHG WR $ ,I ' VZLWFK LV RQ DPRQJ '6 $ EHFRPHV ' SRUW '6 LV FRQQHFWHG WR % ,I ' VZLWFK LV RQ DPRQJ '6 % EHFRPHV ' SRUW ,I ' VZLWFK DPRQJ 6:a6: LV RQ DW ' WKH NH\ a FDQ EH XVHG DV ' SRUW ,I ' VZLWFK DPRQJ 6:a6: LV RQ DW ' WKH NH\ a FDQ EH XVHG DV ' SRUW QRWH WKH SRVLWLRQ RI 6:a DQG 6:a LQ %' LV FKDQJHG 7KH UHIHUHQFH SRVLWLRQ LV ULJKW ,I \RX ZDQW WR LQFUHDVH WKH UHPRWH FRQWUROOHU YDOLG GLVWDQFH \RX WU\ WR GLVFRQQHFW 5 UHVLVWRU DQG OHVVHQ 5 UHVLVWRU 6-12 Chapter 6. Application 5HIHUHQFH WR *06;;;7 %' $WWDFK UHVRQDWRU WR ; $WWDFK $ WUDQVLVWRU WR 4 &RQQHFW 3*1' DQG ' ZLWK MXPSHU DW ( UHPDLQ ' RSHQ VWDWH LQ FDVH RI *067 $WWDFK DERXW . WR 5 & % ( 4 5 5 5 ; ( ' 3*1' 75*1' $ ....5555 % ....5555 '6 & '6 5(0287 75287 26& ' *1' 6:a 6:a '''' '''' '''' '''' . . . . 5 5 5 5 ' ' ' ' ' ' '6 LV FRQQHFWHG WR $ ,I ' VZLWFK LV RQ DPRQJ '6 $ EHFRPHV ' SRUW '6 LV FRQQHFWHG WR % ,I ' VZLWFK LV RQ DPRQJ '6 % EHFRPHV ' SRUW ,I ' VZLWFK DPRQJ 6:a6: LV RQ DW ' WKH NH\ a FDQ EH XVHG DV ' SRUW ,I ' VZLWFK DPRQJ 6:a6: LV RQ DW ' WKH NH\ a FDQ EH XVHG DV ' SRUW QRWH WKH SRVLWLRQ RI 6:a DQG 6:a LQ %' LV FKDQJHG 7KH UHIHUHQFH SRVLWLRQ LV ULJKW ,I \RX ZDQW WR LQFUHDVH WKH UHPRWH FRQWUROOHU YDOLG GLVWDQFH \RX WU\ WR GLVFRQQHFW 5 UHVLVWRU DQG OHVVHQ 5 UHVLVWRU 6-13 GMS36XXX GMS37XXX PACKAGE DIMENSIONS FUNCTIONAL DESCRIPTION INSTRUCTION APPLICATION GMS36XXXT GMS37XXXT EPROM 1 2 3 4 5 6 7 8 9 Chapter 7.GMS36XXXT CHAPTER 7. GMS36XXXT Description The GMS36XXXT series are remote control transmitter which uses CMOS technology and the EPROM version. This enables transmission code outputs of different configurations, multiple custom code output and double push key output for easy fabrication. The GMS36XXXT series are suitable for remote control of TV, VCR, FANS, Air-conditioners, Audio Equipment, Toys, Games etc. Features * * * * * * * * * * * * * * * Program memory : 1,024 bytes for GMS36/004T/112T/140T Data memory : 32 4 bits 43 types of instruction set 3 levels of subroutine nesting Operating frequency : 300kHz ~ 1MHz at kHz version 2.4MHz ~ 4MHz at MHz version Instruction cycle : fOSC/6 at kHz version fOSC/48 at MHz version CMOS process (Single 3.0V power supply) Stop mode (Through internal instruction) Released stop mode by key input Built in Power-on Reset circuit Built in Low Voltage Detection circuit Built in capacitor for ceramic oscillation circuit at kHz version Built in a watch dog timer (WDT) Built in transistor for I.R LED Drive : IOL =190mA at VDD =3V and VO =0.3V Low operating voltage : 2.2 ~ 3.6V (at 300kHz ~ 4MHz) O Table 7-1 GMS36XXXT series members Series Program memory Data memory I/O ports Input ports Output ports Package GMS36004T 1,024 32 GMS36112T 1,024 32 GMS36140T 1,024 32 O4 O4 O4 4 6 (D0~D5) 16DIP/SOP 4 4 6 (D0~D5) 20DIP/SOP/SSOP 4 4 10 (D0~D9) 24Skinny DIP/SOP 7-1 Chapter 7. GMS36XXXT Pin Description Pin VDD GND I/O - Function Connected to 2.2~ 3.6V power supply Connected to 0V power supply. 4-bit input port with built in pull-up resistor. STOP mode is released by "L" input of each pin. Especially, K3 is the input pin for VPP. For programming K3 pin receives 12.5V(programming voltage). Each can be set and reset independently. The output is the structure of N-channel-open-drain. 4-bit I/O port. (Input mode is set only when each of them output "H".) In outputting, each can be set and reset independently(or at once.) The output is in the form of C-MOS. STOP mode is released by "L" input of each pin. Oscillator input. Input to the oscillator circuit and connection point for ceramic resonator. Internal capacitors available at kHz version. A feedback resistor is internally connected between this pin and OSC2. Connect a resonator between this pin and OSC1. High current output port driving I.R. LED. The output is in the form of N-channel-open-drain. High current Tr. ground pin. (connected to GND) High current output Tr. is connected between this pin and REMOUT. K0 ~ K3 Input D0 ~ D9 Output R0 ~ R3 I/O OSC1 Input OSC2 REMOUT Output Output PGND - 7-2 Chapter 7. GMS36XXXT STOP Operation Stop mode can be achieved by STOP instructions. In stop mode : 1. Oscillator is stopped, the operating current is low. 2. Watch dog timer is reset, D0~D3 output is "L"and REMOUT output is "H" (Output Tr. is off.) 3. Part other than WDT, D0~D3 output and REMOUT output have a value before come into stop mode. Stop mode is released when one of K or R input is going to "L". 1. State of D0~D3 output and REMOUT output is return to state of before stop mode is achieved. 2. After 210 OSystem clock time for stable oscillating, first instruction start to operate. 3. In return to normal operation, WDT is counted from zero again. But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction is same to NOP instruction. 7-3 Chapter 7. GMS36XXXT Electrical Characteristics Absolute maximum ratings (Ta = 25I) Parameter Supply Voltage Programming Voltage Power dissipation Storage temperature range Input voltage Output voltage Symbol VDD VPP PD Tstg VIN VOUT Max. rating -0.3 ~ 5.0 -0.3 ~ 13.5 700 * -55 ~ 125 -0.3 ~ V DD+0.3 -0.3 ~ V DD+0.3 Unit V V mW I V V * Thermal derating above 25I : 6mW per degree I rise in temperature. Recommended operating condition Parameter Supply Voltage Operating temperature Symbol VDD Topr Condition 300kHz ~ 4MHz - Rating 2.2 ~ 3.6 -20 ~ +70 Unit V I 7-4 Chapter 7. GMS36XXXT Electrical characteristics (Ta=25I, VDD= 3V) Limits Parameter Symbol Min. Input H current K Pull-up Resistance R Pull-up Resistance Feedback Resistance K, R input H voltage K, R input L voltage D. R output L voltage OSC2 output L voltage OSC2 output H voltage IIH RPU1 RPU2 RFD VIH1 VIL1 VOL2 *1 VOL3 VOH3 IOL1*2 200 REMOUT leakage current D, R output leakage current Current on STOP mode Operating supply current 1 Operating supply current 2 System clock frequency *1 Refer to fOSC/6 fOSC/48 IOLK1 IOLK2 ISTP IDD1 *3 IDD2 *3 fOSC fOSC 300 2.4 250 0.8 1.0 300 1 1 1 1.5 3.0 1000 4 mA uA uA uA mA mA kHz MHz 70 70 0.3 2.1 2.1 150 REMOUT output L current Unit Typ. 140 140 1.0 0.15 0.4 2.5 190 Condition Max. 1 300 300 3.0 0.9 0.4 0.9 230 uA VI=VDD VI=GND VI=GND, Output off VOSC1=GND, VOSC2=VDD I I V V V V V mA IOL2=3mA IOL3=40uA (455kHz) = 150uA (4MHz) IOH3= -40uA (455kHz) = -150uA (4MHz) VOL1=0.3V VOL1=0.4V VOUT=VDD, Output off VOUT=VDD, Output off At STOP mode fOSC=455KHz fOSC=4MHz kHz version MHz version Fig.7-1 *2 Refer to Fig.7-2 IOL2 vs. VOL2 Graph IOL1 vs. VOL1 Graph *3 IDD1, IDD2, is measured at RESET mode. 7-5 Chapter 7. GMS36XXXT A I Fig 7-1. IOL2 vs. VOL2 Graph. ( D, R Port ) I A Fig 7-2. IOL1 vs. VOL1 Graph. ( REMOUT port) 7-6 GMS36XXX GMS37XXX PACKAGE DIMENSIONS FUNCTIONAL DESCRIPTION INSTRUCTION APPLICATION GMS36XXXT GMS37XXXT EPROM 1 2 3 4 5 6 7 8 9 Chapter 8. GMS37XXXT CHAPTER 8. GMS37XXXT Description The GMS37XXXT series are remote control transmitter which uses CMOS technology and the EPROM version. This enables transmission code outputs of different configurations, multiple custom code output, and double push key output for easy fabrication. The GMS37XXXT series are suitable for remote control of TV, VCR, FANS, Airconditioners, Audio Equipment, Toys, Games etc. It is possible to structure the 8 x 7 key matrix for GMS37112T, and the 4 x 7 key matrix for GMS37004T. Features * * * * * * * * * * * * * * Program memory : 1,024 bytes for GMS37004T/112T/140T Data memory : 32 4 bits 43 types of instruction set 3 levels of subroutine nesting Operating frequency : 300kHz ~ 1MHz at kHz version 2.4MHz ~ 4MHz at MHz version Instruction cycle : fOSC/6 at kHz version fOSC/48 at MHz version CMOS process (Single 3.0V power supply) Stop mode (Through internal instruction) Released stop mode by key input Built in Power-on Reset circuit Built in Low Voltage Detection circuit Built in capacitor for ceramic oscillation circuit at kHz version Built in a watch dog timer (WDT) Low operating voltage : 2.2 ~ 3.6V (at 300kHz ~ 4MHz) O Table 8-1 GMS37XXXT series members Series Program memory Data memory I/O ports Input ports Output ports Package GMS37004T 1,024 32 GMS37112T 1,024 32 GMS37140T 1,024 32 O4 O4 O4 4 7 (D0~D6) 16DIP/SOP 4 4 7 (D0~D6) 20DIP/SOP/SSOP 4 4 10 (D0~D9) 24Skinny DIP/SOP 8-1 Chapter 8. GMS37XXXT Pin Description Pin VDD GND I/O - Function Connected to 2.2~ 3.6V power supply Connected to 0V power supply. 4-bit input port with built in pull-up resistor. STOP mode is released by "L" input of each pin. Especially, K3 is the input pin for VPP. For programming K3 pin receives 12.5V(programming voltage). Each can be set and reset independently. The output is the structure of N-channel-open-drain. K0 ~ K3 Input D0 ~ D9 Output R0 ~ R3 I/O 4-bit I/O port. (Input mode is set only when each of them output "H".) In outputting, each can be set and reset independently(or at once.) The output is in the form of C-MOS. STOP mode is released by "L" input of each pin. Oscillator input. Input to the oscillator circuit and connection point for ceramic resonator. Internal capacitors available at kHz version. A feedback resistor is internally connected between this pin and OSC2. Connect a resonator between this pin and OSC1. High current output port The output is in the form of C-MOS. The state of large current on is " H " OSC1 Input OSC2 Output REMOUT Output 8-2 Chapter 8. GMS37XXXT STOP Operation Stop mode can be achieved by STOP instructions. In stop mode : 1. Oscillator is stopped, the operating current is low. 2. Watch dog timer is reset, D0~D3 output is "L"and REMOUT output is "L" 3. Part other than WDT, D0~D3 output and REMOUT output have a value before come into stop mode. Stop mode is released when one of K or R input is going to "L". 1. State of D0~D3 output and REMOUT output is return to state of before stop mode is achieved. 2. After 210 OSystem clock time for stable oscillating, first instruction start to operate. 3. In return to normal operation, WDT is counted from zero again. But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction is same to NOP instruction. 8-3 Chapter 8. GMS37XXXT Electrical Characteristics Absolute maximum ratings (Ta = 25I) Parameter Supply Voltage Programming Voltage Power dissipation Storage temperature range Input voltage Output voltage Symbol VDD VPP PD Tstg VIN VOUT Max. rating -0.3 ~ 5.0 -0.3 ~ 13.5 700 * -55 ~ 125 -0.3 ~ V DD+0.3 -0.3 ~ V DD+0.3 Unit V V mW I V V * Thermal derating above 25I : 6mW per degree I rise in temperature. Recommended operating condition Parameter Supply Voltage Operating temperature Symbol VDD Topr Condition 300kHz ~ 4MHz - Rating 2.2 ~ 3.6 -20 ~ +70 Unit V I 8-4 Chapter 8. GMS37XXXT Electrical characteristics (Ta=25I, VDD= 3V) Limits Parameter Symbol Min. Input H current K Pull-up Resistance R Pull-up Resistance Feedback Resistance K, R input H voltage K, R input L voltage D. R output L voltage OSC2 output L voltage OSC2 output H voltage REMOUT output L current REMOUT output H current D, R output leakage current Current on STOP mode Operating supply current 1 Operating supply current 2 System clock frequency fOSC/6 fOSC/48 IIH RPU1 RPU2 RFD VIH1 VIL1 VOL2 *1 Unit Typ. 140 140 1.0 0.15 0.4 2.5 2.2 -15 0.8 1.0 - Condition Max. 1 300 300 3.0 0.9 0.4 0.9 4 -30 1 1 1.5 3.0 1000 4 uA VI=VDD VI=GND VI=GND, Output off VOSC1=GND, VOSC2=VDD 70 70 0.3 2.1 2.1 1 -5 300 2.4 I I V V V V V mA mA uA uA mA mA kHz MHz IOL2=3mA IOL3=40uA (455kHz) =150uA (4MHz) IOH3= -40uA (455kHz) = -150uA (4Mhz) VOL1=0.4V VOH1=2V VOUT=VDD, Output off At STOP mode fOSC=455KHz fOSC=4MHz kHz version MHz version VOL3 VOH3 IOL1 *2 IOH1 *3 IOLK2 ISTP IDD1 *4 IDD2 *4 fOSC fOSC *1 Refer to Fig.8-1 < IOL2 vs. VOL2 Graph> *2 Refer to Fig.8-2 < IOL1 vs. VOL1 Graph> *3 Refer to Fig.8-3 < IOH1 vs. VOH1 Graph> *4 IDD1, IDD2, is measured at RESET mode. 8-5 Chapter 8. GMS37XXXT I |A} |} Fig 8-1. IOL2 vs. VOL2 Graph. ( D, R, OD6 Port ) I |A} |} Fig 8-2. IOL1 vs VOL1 Graph (REMOUT Port) 8-6 Chapter 8. GMS37XXXT I |A} |} Fig 8-3. IOH1 vs VOH1 Graph (REMOUT Port) 8-7 GMS36XXX GMS37XXX PACKAGE DIMENSIONS FUNCTIONAL DESCRIPTION INSTRUCTION APPLICATION GMS36XXXT GMS37XXXT EPROM 1 2 3 4 5 6 7 8 9 Chapter 9. EPROM CHAPTER 9. EPROM MODE Define Item User mode EPROM read mode 1Byte PGM Write & Verify Lock bit Write mode Lock bit Read mode Reset mode Device operation Exact User pgm Address in, Data out Address in, Data in Data out Lock bit write Lock bit out (to D5 port) System reset before all test Mode setting K3~ K0 = 0 ~ 3V K1~0=01/10 K1~0=01/10 K3 =12.5V K2 = Vcc K1~0=01/00 K1~0=01/01 K2 = 0V Vcc=5.5V, (Default : unlock) Vcc=3V Vcc=5.5V Vcc=5.5V - * Mode setting (K1~0=01/10) means the serial input by 2bits. Port Define for GMS36XXXT (SURP 0RGH 8VHU 0RGH *1' &ORFN 8VHU 0RGH (SURP 0RGH *1' 26& 26& ' ' . . . . 5 5 5 9'' 5(0287 3*1' ' ' ' ' ' ' ' ' 5 9'' 3RUW 1DPH 8VHU 0RGH (3520 0RGH 9''*1' /RFN GDWD RXW $G$G $G$G 'D'D $G$G 'D'D $G$G 'D'D $G$G 'D'D 3RZHU 3JQG 9 &ORFN 5HPRXW .,QSXW .,QSXW .,QSXW .,QSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW 5,2 5,2 5,2 5,2 $G $G $G $G $G 3RZHU &ORFN 0RGH VHWWLQJ 5HDG :ULWH &RQWURO 00 00 5HVHW 933 3,1 *067 3*1' 26& 5HPRXW . . . $GGUHVV 'DWD &RQWURO 5HVHW 933 9 $G $G $G $G $G 'D 'D 'D 'D 'D 'D 'D 'D *1' &ORFN *1' 26& 26& . . . . 5 5 5 9'' 5(0287 3*1' ' ' ' ' ' ' 5 . 9'' ' ' 00 00 5HVHW 933 3,1 *067 /RFN GDWD RXW $G$G $G$G 'D'D $G$G 'D'D $G$G 'D'D $G$G 'D'D ' ' ' ' ' ' /RFN GDWD RXWSXW *1' &ORFN *1' 26& 26& . . . . ' 9'' 5(0287 3*1' ' ' ' ' ' ' 9'' ' 5 00 00 5HVHW 933 'D'D $G$G 3,1 *067 /RFN GDWD RXW $G$G $G$G 'D'D $G$G 'D'D $G$G 'D'D 5 5 5 9-1 Chapter 9. EPROM Port Define for GMS37XXXT (SURP 0RGH 8VHU 0RGH *1' &ORFN 8VHU 0RGH (SURP 0RGH *1' 26& 26& ' ' . . . . 5 5 5 9'' 5(0287 1& ' ' ' ' ' ' ' ' 5 9'' 3RUW 1DPH 8VHU 0RGH (3520 0RGH 9''*1' /RFN GDWD RXW $G$G $G$G 'D'D $G$G 'D'D $G$G 'D'D $G$G 'D'D 3RZHU &ORFN .,QSXW .,QSXW .,QSXW .,QSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW '2XWSXW 5HPRXW 5,2 5,2 5,2 5,2 $G $G $G $G $G 3RZHU &ORFN 0RGH VHWWLQJ 5HDG :ULWH &RQWURO 00 00 5HVHW 933 3,1 *067 26& . . . . ' $GGUHVV 'DWD &RQWURO 5HVHW 933 9 $G $G $G $G $G 'D 'D 'D 'D 'D 'D 'D 'D *1' &ORFN *1' 26& 26& . . . . 5 5 5 9'' 5(0287 ' ' ' ' ' ' ' 5 ' 9'' ' ' 00 00 5HVHW 933 3,1 *067 /RFN GDWD RXW $G$G $G$G 'D'D $G$G 'D'D $G$G 'D'D $G$G 'D'D ' ' ' ' ' ' /RFN GDWD RXWSXW *1' &ORFN *1' 26& 9'' 5(0287 ' ' ' ' ' ' 1& 9'' 5HPRXW 5 26& . . . . ' 00 00 5HVHW 933 'D'D $G$G 3,1 *067 /RFN GDWD RXW $G$G $G$G 'D'D $G$G 'D'D $G$G 'D'D 5 5 5 9-2 Chapter 9. EPROM AC / DC Timing Requirements for Program / Read Mode (Ta = 25I ) 1D PH 6\ PER O 8QLWV XV 26& &OR FN 3HULRG 7S QV 3UR JUD PPLQJ 6XSSO\ &XUUH QW 6XSSO\ &XUUHQW LQ (3520 0RGH 933 /H Y HO GXULQJ 3UR JUD PPLQJ 9'' /H Y H O LQ 3UR JUD P 0R GH 9'' /H Y H O LQ 5HD G 0R GH . a . +LJK /HY H O LQ (3520 0R GH . a . /R Z /H Y HO LQ (3520 0R GH 'a' +LJK /H YH O LQ (3520 0RGH 'a' +LJK /H YH O LQ (3520 0RGH 9'' 6WXUD WLRQ 7LPH 933 6H WXS 7LPH 933 6D WXUD WLR Q 7LPH . ,QSXW 'H OD \ WLPH . ,QSXW 6H WXS WLPH .a. 0RGH LQSXW 6H WXS WLPH 'a' 'D WD LQSXW +ROG 7LPH .a. 'D WD LQSXW 6H WXS 7LPH 'a' 'D WD LQSXW 6H WXS 7LPH 'a' 2XWSXW 6WUR ELQJ 7LPH ' 2XWSXW 6WUR ELQJ 7LPH ,933 ,9''3 9,+3 9''+ 9''+ 9,+. 9,/. 9,+' 9,/' 79''6 79335 79336 7.' 7.6 702'( 7+/' 7'/< 7'/< 767% 767% P$ P$ 9 9 9 9 9 9 9 PV PV PV QV QV XV XV QV QV QV XV 9'' [ 9'' [ 7S 7S 7S [ 7S [ 7S [ 7S [ 7S [ 7S 7S 7S [ 7S 7S [ 7S [ 7S [ 7S [ 9'' [ 9'' [ 7S 7S 7S [ 7S [ 7S [ 7S [ 7S [ $W /R FN 5H D G 2QO\ 6\ VWH P UH VH W D W 0+= 9H UVLR Q 0LQ 7\ S 0D[ I D W .+= 9H UVLRQ L 9-3 Chapter 9. EPROM Program / Verify Timing Diagrams In kHz Version. 1) EPROM Write & Verify Mode (1Byte) 73 26& 9''+ 9'' 79336 .933 9,+3 79335 7.6 9''+ . 7.' .a. 702'( 7'/< 0/ 7'/< 0+ 'a' 5HVHW (SURP :ULWH 0RGH VHWWLQJ $+ $/ '+ '/ 2+ 2/ $+ $/ '+ '/ 7+/' WLPHV UHSHDW XV [ XV 767% 7+/' $GGU $GGU $+ +LJK ELW $GGUHVV ,QSXW /DWFK $/ /RZ ELW $GGUHVV ,QSXW /DWFK 0+ +LJK ELW 0 RGH , QSXW /DWFK '+ +LJK ELW 'DWD ,QSXW /DWFK '/ /RZ ELW 'DWD ,QSXW /DWFK 0/ /RZ ELW 0RGH ,QSXW /DWFK 2+ +LJK ELW 'DWD 2XWSXW 2/ /RZ ELW 'DWD 2XWSXW #. Note : 1. Internal system is reset at VPP = 12.5V and K2=Low 2. The reset release (K2=High) must be set within OSC1 = Low state. (From this time, OSC1 clock is counted.) 3. The Data will be inputted from the 19th rising edge of OSC1. 4. If not written during 10 times repeats (120us), repeat the 5 times until all is written. 5. For device verify. If you set Lock bit, output data is always 0Fh. 9-4 Chapter 9. EPROM 2) EPROM Read Mode (1Byte) 73 26& 9''+ 9'' 79336 .933 9,+3 79335 7.6 9''+ . 7.' .a. 702'( 0/ 7'/< 0+ 7'/< 'a' 5HVHW (SURP 5HDG 0RGH VHWWLQJ $+ $/ 2+ 2/ $+ $/ 2+ 2/ $+ $/ 2+ 2/ $+ $/ 2+ 7+/' 767% 7+/' 767% 7+/' 767% 7+/' 767% $GGU $GGU $GGU $GGU $+ +LJK ELW $GGUHVV ,QSXW /DWFK $/ /RZ ELW $GGUHVV ,QSXW /DWFK 0+ +LJK ELW 0 RGH , QSXW /DWFK '+ +LJK ELW 'DWD ,QSXW /DWFK '/ /RZ ELW 'DWD ,QSXW /DWFK 0/ /RZ ELW 0RGH ,QSXW /DWFK 2+ +LJK ELW 'DWD 2XWSXW 2/ /RZ ELW 'DWD 2XWSXW #. Note : 1. Internal system is reset at VPP = 12.5V and K2=Low 2. The reset release (K2=High) must be set within OSC1 = Low state. (From this time, OSC1 clock is counted.) 3. The Data will be inputted from the 19th rising edge of OSC1. 4. For device verify. If you set Lock bit, output data is always 0Fh. 9-5 Chapter 9. EPROM 3) Lock Bit Write Mode 73 26& 9''+ 9'' 79336 .933 9,+3 79335 7.6 9''+ 702'( 7'/< 7'/< 7'/< . 7.' .a. 0+ 0/ 'a' :DLW F\FOH 5HVHW /RFN :ULWH 0RGH VHWWLQJ XV [ XV WLPHV UHSHDW 0+ +LJK ELW 0 RGH , QSXW /DWFK 0/ /RZ ELW 0RGH ,QSXW /DWFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=Low 2. The reset release (K2=High) must be set within OSC1 = Low state. (From this time, OSC1 clock is counted.) 3. If not written during 10 times repeats (120us), repeat the 5 times until all is written. 9-6 Chapter 9. EPROM 4) Lock Bit Read Mode 73 26& 9''+ 9'' 79336 .933 9,+3 79335 7.6 9''+ . 7.' .a. 702'( 0/ 0+ 'a' ' 5HVHW /RFN 5HDG 0RGH VHWWLQJ /RFN ELW RXWSXW 767% 0+ +LJK ELW 0 RGH , QSXW /DWFK 0/ /RZ ELW 0RGH ,QSXW /DWFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=Low 2. The reset release (K2=High) must be set within OSC1 = Low state. (From this time, OSC1 clock is counted.) 3. Lock data is outputted from D5 port. If you set Lock bit, the output data of D5 is always H. 9-7 Chapter 9. EPROM Program / Verify Timing Diagrams In MHz Version. 1) EPROM Write & Verify Mode (1Byte) %ORFN %ORFN %ORFN %ORFN %ORFN 73 [ 73 26& 9''+ 9'' 79336 79335 9,+3 7.6 7.' .933 9''+ 702'( . 7'/< 7'/< .a. 0+ 0/ 'a' $+ 7+/' 5HVHW (SURP :ULWH 0RGH VHWWLQJ $GGU $+ +LJK ELW $GGUHVV ,QSXW /DWFK '+ +LJK ELW 'DWD ,QSXW /DWFK 2+ +LJK ELW 'DWD 2XWSXW $/ /RZ ELW $GGUHVV ,QSXW /DWFK '/ /RZ ELW 'DWD ,QSXW /DWFK 2/ /RZ ELW 'DWD 2XWSXW 0+ +LJK ELW 0RGH ,QSXW /DWFK 0/ /RZ ELW 0RGH ,QSXW /DWFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=Low 2. OSC1 is made of a block of 8 x Tp clock. 3. From this time when the reset is released (K2=High) , OSC1 clock is counted by 1-bolck. 4. If not written during 10 times repeats (120us), repeat the 5 times until all is written. 5. For device verify. If you set Lock bit, output data is always 0Fh. &RQWLQXH WR 1H[W 3DJH 9-8 Chapter 9. EPROM - Continue - %ORFN %ORFN %ORFN %ORFN %ORFN 26& 9''+ 9'' .933 . .a. 9,+3 9''+ 7'/< 7'/< 7'/< $/ 7+/' '+ 7+/' $GGU 7'/< '/ 7+/' 'a' $+ 7+/' %ORFN %ORFN %ORFN %ORFN 26& 9''+ 9'' .933 . .a. 9,+3 9''+ 7'/< 7'/< 7'/< 7'/< 'a' WLPHV UHSHDW XV [ XV 2+ 767% $GGU 2/ 767% $+ $GGU 9-9 Chapter 9. EPROM 2) EPROM Read Mode %ORFN %ORFN %ORFN %ORFN %ORFN 73 [ 73 26& 9''+ 9'' 79336 79335 9,+3 7.6 7.' .933 9''+ 702'( . 7'/< 7'/< .a. 0+ 0/ 'a' $+ 7+/' 5HVHW (SURP 9HULI\ 0RGH VHWWLQJ $GGU $+ +LJK ELW $GGUH VV ,QSXW /D WFK $/ /R Z ELW $GGUH VV ,QSXW /D WFK '+ +LJK ELW 'D WD ,QSXW /D WFK '/ /R Z ELW 'D WD ,QSXW /D WFK 2+ +LJK ELW 'D WD 2XWSXW 2/ /R Z ELW 'D WD 2XWSXW 0+ +LJK ELW 0R GH ,QSXW /D WFK 0/ /R Z ELW 0RGH ,QSXW /D WFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=Low 2. OSC1 is made of a block of 8 x Tp clock. 3. From this time when the reset is released (K2=High) , OSC1 clock is counted by 1-bolck. 4. For device verify. If you set Lock bit, output data is always 0Fh. &RQWLQXH WR 1H[W 3DJH 9-10 Chapter 9. EPROM - Continue %ORFN %ORFN %ORFN %ORFN %ORFN 26& 9''+ 9'' .933 . .a. 9,+3 9''+ 7'/< 7'/< 'a' $+ 7+/' $/ 7+/' $GGU 2+ 767% 767% 2/ %ORFN %ORFN %ORFN %ORFN 26& 9''+ 9'' .933 . 7 '/< .a. 7'/< 7'/< $+ 7+/' $/ 7+/' 9,+3 9''+ 7'/< 'a' 2/ 2+ 767% $GGU 9-11 Chapter 9. EPROM 3) Lock Bit Write Mode %ORFN %ORFN %ORFN %ORFN %ORFN 73 [ 73 26& 9''+ 9'' 79336 79335 9,+3 7.6 7.' .933 9''+ 702'( 0/ . .a. 0+ 'a' 5HVHW /RFN :ULWH 0RGH VHWWLQJ :DLW F\ FOH %ORFN %ORFN %ORFN %ORFN 26& 9''+ 9'' .933 . .a. 9,+3 9''+ 7'/< 7'/< 'a' WLPHV UHSHDW :DLW F\ FOH XV [ XV 0+ +LJK ELW 0RGH ,QSXW /DWFK 0/ /RZ ELW 0RGH ,QSXW /DWFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=Low 2. OSC1 is made of a block of 8 x Tp clock. 3. From this time when the reset is released (K2=High) , OSC1 clock is counted by 1-bolck. 4. If not written during 10 times repeats(120us), repeat the 5 times until all is written. 9-12 Chapter 9. EPROM 4) Lock Bit Read Mode %ORFN %ORFN %ORFN %ORFN %ORFN 73 [ 73 26& 9''+ 9'' 79336 79335 9,+3 7.6 7.' .933 9''+ 702'( 0/ . .a. 0+ 'a' /RFN ELW 2XWSXW 5HVHW /RFN 5HDG 0RGH VHWWLQJ ' 767% 0+ +LJK ELW 0RGH ,QSXW /DWFK 0/ /RZ ELW 0RGH ,QSXW /DWFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=Low 2. OSC1 is made of a block of 8 x Tp clock. 3. From this time when the reset is released (K2=High) , OSC1 clock is counted by 1-bolck. 4. Lock data is outputted from D5 port. If you set Lock bit, the output data of D5 is always H. 9-13 Chapter 9. EPROM Caution when programming Writing should be done at the defined voltage and timing. In case of EPROM mode, programming voltage is 12.5V. More than defined voltage can give device so great damage to destroy it. Before writing you had better ascertain the characteristics of socket and socket adapter of EPROM writer. It can happen to write error when you touch socket adapter or device. We recommend below flow to improve reliability after writing. :ULWH XVLQJ WKH (3520 :ULWHU 6FUHHQLQJ I KRXUV 9HULI\ 7HVW XVLQJ (3520 :ULWHU )XQFWLRQ 7HVW XVLQJ 0DQXDO 7HVW Y Timing Flowchart for Eprom Program / Verify. 67$57 &KDQJH WKH P RGH 5HVHW 6HW (SURP 5HDG PRGH 9 '' 9 33 9 9 933 9 9'' 9 5HVHW 9 '' 9 33 9 9 UHDG DOO DGGUHVV %ODQN 9HULI\ IDLO 5HSRUW %ODQN 9HULI\ )DLOXUH 6HW (SURP 5HDG PRGH SDVV &KDQJH WKH P RGH 933 9 9'' 9 IDLO UHDG DOO DGGUHVV SDVV 5HVHW 6HW (3520 ZULWH PRGH 9 '' 9 33 9 9 5HSRUW 9HULI\ )DLOXUH 5HSRUW 3URJUDPPLQJ 2. )LUVW $GGUHVV Q Q a Q \HV Q " QR 5HSRUW 3URJUDPPLQJ )DLOXUH (SURP :ULWH 5HSHDW XQWLO QHDU XV XV XV #N+] IDLO 9HULI\ SDVV 6HW 933 6HW 9'' 9 9 (SURP :ULWH :ULWH RQH PRUH WLPH (1' DGGUHVV a DGGUHVV QR ODVW DGGUHVV " \HV 9-14 Chapter 9. EPROM Y Timing Flowchart for Lock Bit Program / Verify. 67$57 &KDQJH WKH P RGH 933 9 9'' 9 5HVHW 6HW /RFN %LW ZULWH PRGH 9 '' 9 33 9 9 5HVHW 6HW /RFN %LW 5HDG PRGH 9 '' 9 33 9 9 :DLW F\FOH IDLO UHDG /RFN %LW' Q SDVV Q a &KDQJH WKH P RGH Q 933 9 9'' 9 /RFN %LW :ULWH 5HSHDW XQWLO QHDU XV XV XV #N+] 5HVHW 6HW /RFN %LW 5HDG PRGH 9 '' 9 33 9 9 1R Q " IDLO UHDG /RFN %LW' 5HSRUW /RFN %LW 3URJUDPPLQJ 2. 5HSRUW /RFN %LW 5HDG )DLOXUH 6HW 933 6HW 9'' 9 9 (1' 9-15 MASK ORDER & VERIFICATION SHEET GMS3 -R 1. Customer Information Company Name Name & Signature 2. Device Information 16 SOP (150mil) 16 SOP (300mil) 20 SSOP 24 DIP Tel: Order Date Fax: ( . RHX ) . DMP @27C256 Package 16 DIP 20 DIP 20 SOP 24 SOP Mask Data File Name Check Sum 3. Mask Option Inclusion of Pull-up Register Status of D port while Stop mode Port R0* R1* R2* R3* Y/N Release of Stop mode Port K0 K1 K2 K3 R0* R1* R2* R3* Y/N System Clock Selection Port D0 D1 D2 D3 D4 D5 D6 D7**D8**D9** a/b focs / 6 fosc / 48 Inclusion of condensor for Osc. Y/N 1. Don't use WDTR instruction in subroutine. 2. Use Br $ at start (except 0 page ) , end and unused address in every page. 3. a: State of " L" forcibly, b: Remain the state just before stop instruction. You must select "a" option when you use Dport as key application. 4. If you use fosc/6, we recommend inclusion of condensor and fosc/48, no inclusion of condensor * : Marked port is not available for GMS36/37004 ** : Marked port is not available for GMS36/37004/112 5. D6 port is available for GMS37004/112 but not available for GMS36004/112 4. Marking Specification Standard Marking HYNIX User Marking User LOGO R 5. Delivery Schedule YWW R YWW Date Mask Sample Risk Order . . . . Quantity pcs pcs Confirmation 6. ROM CODE Verification HYNIX Semiconductor Inc. write in below Verification Date : Please confirm our verification data. Customer write in below Approval Date : . . Check Sum : @27c256 TEL :82-431-270-4078 FAX :82-431-270-4075 Name & HYNIX Semiconductor Inc. Signature MCU APPLICATION TEAM I agree with your verification data and confirm you to make mask set. TEL : Company Name : Section Name : Signature : FAX : |
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